C8051F960-B-GM Datasheet, PDF (298/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 24.1. RTC0KEY: SmaRTClock Lock and Key
Bit
7
6
5
4
3
2
1
0
Name
RTC0ST[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAE
Bit Name
7:0 RTC0ST SmaRTClock Interface Status.
Provides lock status when read.
Function
Read:
0x02: SmaRTClock Interface is unlocked.
Write:
Writes to RTC0KEY have no effect.
SFR Definition 24.2. RTC0ADR: SmaRTClock Address
Bit
7
6
5
4
3
2
1
0
Name
AUTORD
ADDR[4:0]
Type
R
R/W
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAC
Bit Name
Function
7 Reserved Read = 0; Write = don’t care.
6 AUTORD SmaRTClock Interface Autoread Enable.
Enables/disables Autoread.
0: Autoread Disabled.
1: Autoread Enabled.
5 Unused Read = 0b; Write = Don’t Care.
4:0 ADDR[4:0] SmaRTClock Indirect Register Address.
Sets the currently selected SmaRTClock register.
See Table 24.1 for a listing of all SmaRTClock indirect registers.
Note: The ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMnBn
internal SmaRTClock register.
298
Rev. 1.0