C8051F960-B-GM Datasheet, PDF (185/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
14.4. AES Block Cipher Data Flow
The AES0 module data flow for AES Block Cipher encryption and decryption shown in Figure 14.3. The
data flow is the same for encryption and decryption. The AES0DCF sfr is always configured to route the
AES core output to AES0YOUT. The XOR on the input and output paths are not used.
For an encryption operation, the core is configured for an encryption cipher, the encryption key is written to
AES0KIN, the plaintext is written to the AES0BIN sfr. and the ciphertext is read from AES0YOUT.
For a decryption operation, the core is configured for an decryption cipher, the decryption key is written to
AES0KIN, the ciphertext is written to the AES0BIN sfr. and the plaintext is read from AES0YOUT.
The key size is set to the desired key size.
AES0BIN
internal state
machine
AES0XIN
+
AES0DCFG
AES0KIN
Data In
Key
AES
Key
In
Core
Out
Data Out
AES0BCFG
+
AES0YOUT
Figure 14.3. AES Block Cipher Data Flow
Rev. 1.0
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