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C8051F960-B-GM Datasheet, PDF (200/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family | |||
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C8051F96x
14.6.6. CTR Encryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use with the code examples. The steps are documented in the data sheet for complete-
ness.
ï® Prepare encryption Key, counter, and data to be encrypted in xram.
ï® Reset AES module by clearing bit 2 of AES0BCFG.
ï® Disable the first four DMA channels by clearing bits 0 to 3 in the DMA0EN sfr.
ï® Configure the first DMA channel for the AES0KIN sfr
ï¬ï Select the first DMA channel by writing 0x00 to the DMA0SEL sfr
ï¬ï Configure the first DMA channel to move xram to AES0KIN sfr by writing 0x05 to the DMA0NCF sfr
ï¬ï Clear DMA0NMD to disable wrapping.
ï¬ï Write the xram location of encryption key to the DMA0NBAH and DMA0NBAL sfrs.
ï¬ï Write the key length in bytes to DMA0NSZL sfr
ï¬ï Clear the DMA0NSZH sfr
ï¬ï Clear the DMA0NAOH and DMA0NAOL sfrs
ï® Configure the second DMA channel for the AES0BIN sfr.
ï¬ï Select the second DMA channel by writing 0x01 to the DMA0SEL sfr.
ï¬ï Configure the second DMA channel to move xram to AES0BIN sfr by writing 0x06 to the DMA0NCF sfr.
ï¬ï Clear DMA0NMD to disable wrapping.
ï¬ï Write the xram address of the data to be encrypted to the DMA0NBAH and DMA0NBAL sfrs.
ï¬ï Write 16 to the DMA0NSZL SFR for one block of 16 bytes.
ï¬ï Clear the DMA0NSZH sfr
ï¬ï Clear the DMA0NAOH and DMA0NAOL sfrs.
ï® Configure the third DMA channel for the AES0XIN sfr.
ï¬ï Select the third DMA channel by writing 0x02 to the DMA0SEL sfr.
ï¬ï Configure the third DMA channel to move xram to AES0XIN sfr by writing 0x07 to the DMA0NCF sfr.
ï¬ï Clear DMA0NMD to disable wrapping.
ï¬ï Write the xram address of counter to the DMA0NBAH and DMA0NBAL sfrs.
ï¬ï Write 16 to the DMA0NSZL SFR for one block of 16 bytes.
ï¬ï Clear the DMA0NSZH sfr
ï¬ï Clear the DMA0NAOH and DMA0NAOL sfrs.
ï® Configure the fourth DMA channel for the AES0YOUT sfr
ï¬ï Select the fourth channel by writing 0x03 to the DMA0SEL sfr
ï¬ï Configure the fourth DMA channel to move the contents of the AES0YOUT sfr to xram by writing 0x08 to the
DMA0NCF sfr
ï¬ï Enable transfer complete interrupt by setting bit 7 of DMA0NCF sfr
ï¬ï Clear DMA0NMD to disable wrapping
ï¬ï Write 16 to the DMA0NSZL SFR for one block of 16 bytes.
ï¬ï Clear the DMA0NSZH sfr
ï¬ï Clear the DMA0NAOH and DMA0NAOL sfrs.
ï® Clear first four DMA interrupts by clearing bits 0 to 3 in the DMA0INT sfr.
ï® Enable first four DMA channels setting bits 0 to 3 in the DMA0EN sfr
ï® Configure the AES Module data flow for XOR on output data by writing 0x02 to the AES0DCFG sfr.
ï® Write key size to bits 1 and 0 of the AES0BCFG
ï® Configure the AES core for encryption by setting the bit 2 of AES0BCFG
ï® Initiate the encryption operation be setting bit 3 of AES0BCFG
ï® Wait on the DMA interrupt from DMA channel 3
ï® Disable the AES Module by clearing bit 2 of AES0BCFG
200
Rev. 1.0
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