C8051F960-B-GM Datasheet, PDF (462/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Setting TF3CEN to 1 enables the SmaRTClock/External Oscillator Capture Mode for Timer 3. In this mode,
T3SPLIT should be set to 0, as the full 16-bit timer is used.
When Capture Mode is enabled, a capture event will be generated either every SmaRTClock rising edge
or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the
contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL)
and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are enabled). By recording the differ-
ence between two successive timer capture values, the SmaRTClock or external clock period can be
determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture
clock to achieve an accurate reading.
For example, if T3ML = 1b, T3XCLK1 = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSCLK and cap-
ture every SmaRTClock rising edge. If SYSCLK is 24.5 MHz and the difference between two successive
captures is 350 counts, then the SmaRTClock period is as follows:
350 x (1 / 24.5 MHz) = 14.2 µs.
This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or
the time between consecutive SmaRTClock rising edges, which is useful for determining the SmaRTClock
frequency.
T 3 X C L K [1 :0 ]
S Y S C L K /1 2
X0
External Clock/8
01
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL
10
Sm aRTClock
11
0
TR3
SYSCLK
1
T3XCLK1
TF3CEN
Sm aRTClock
0
TCLK
C a p tu re
TMR3L
TMR3H
TMR3RLL TMR3RLH
External Clock/8
1
Figure 32.9. Timer 3 Capture Mode Block Diagram
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK1
T3XCLK0
Interrupt
462
Rev. 1.0