C8051F960-B-GM Datasheet, PDF (205/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 14.4. AES0XIN: AES XOR Input
Bit
7
6
5
4
3
2
1
0
Name
AES0XIN[7:0]
Type ^R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xEC; SFR page = 0x2; Not bit-Addressable
Bit
Name
Function
7:0 AES0XIN[7:0] AES XOR Input.
The AES0XIN may be used in conjunction with the AES0BIN sfr for some cipher
block modes.
When used with the DMA, the DMA will write directly to this sfr.
When used without the DMA - AES0BIN, AES0XIN, and AES0KIN must be written
in sequence.
Reading this register will yield the last value written. This can be used for debug
purposes.
SFR Definition 14.5. AES0KIN: AES Key Input
Bit
7
6
5
4
3
2
1
0
Name
AES0KIN[7:0]
Type ^R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xED; SFR page = 0x2; Not bit-Addressable
Bit
Name
Function
7:0 AES0KIN[7:0] AES Key Input.
During an encryption operation, the plaintext is written to the AES0BIN sfr. During
an decryption operation, the ciphertext is written to the AES0BIN sfr. During a key
inversion the encryption key is written to AES0BIN.
When used with the DMA, the DMA will write directly to this sfr.
The AES0BIN may be used in conjunction with the AES0XIN sfr for some cipher
block modes.
When used without the DMA - AES0BIN, AES0XIN, and AES0KIN must be written
in sequence.
Rev. 1.0
205