C8051F960-B-GM Datasheet, PDF (202/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 14.1. AES0BCFG: AES Block Configuration
Bit
7
Name
Type
R
Reset
0
6
5
4
3
2
DONE
BUSY
EN
ENC
R
R/W
R
R/W
R/W
0
0
0
0
0
1
0
KSIZE
R/W
0
0
SFR Address = 0xE9; SFR page = 0x2; Not bit-Addressable
Bit Name
Function
5 DONE Done Flag.
This bit is set upon completion of an encryption operation. When used with the DMA,
the DONE bit signals the start of the out transfer. When used without the DMA, the
done flag indicates data is ready to be read from AES0YOUT. The DONE bit is not
cleared by hardware and must be cleared to zero by software at the start of the next
encryption operation.
4 BUSY AES BUSY.
This bit is set while the AES block is engaged in an encryption or decryption operation.
This bit is read only.
3
EN AES Enable.
This bit should be set to 1 to initiate an encryption or decryption operation. Clearing this
bit to 0 will reset the AES module.
2
ENC Encryption/Decryption Select.
This is set to 1 to select an encryption operation. Clearing this bit to 0 will select a
decryption operation.
1:0 KSIZE[1:0] AES Key Size.
These bits select the key size for encryption/decryption. The encryption/decryption time
depends on the key size selected.
00: Select 128-bits (16-bytes). Encryption/decryption takes 218 clocks.
01: Select 198-bits (24-bytes). Encryption/decryption takes 274 clocks.
10: Select 256-bits (32-bytes). Encryption/decryption takes 298 clocks.
11: Reserved
202
Rev. 1.0