C8051F960-B-GM Datasheet, PDF (214/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 15.1. ENC0CN: Encoder Decoder 0 Control
Bit
7
6
5
4
3
Name ^{READY ERROR}
ENC
DEC
Type
R
R
R/W
R/W
R
Reset
0
0
0
0
0
SFR Address = 0xC5; SFR page = 0x2; Not bit-Addressable
Bit Name
Function
7 READY _{Ready Flag.}
2
DMA
R/W
0
1
ENDIAN
R/W
0
0
MODE
R/W
0
6 ERROR _{Error Flag.}
5
ENC _Encode.
Setting this bit will initiate an Encode operation.
4
DEC _Decode.
Setting this bit will initiate a Decode operation.
2
DMA _{DMA Mode Enable.}
This bit should be set when using the encoder/decoder with the DMA.
1 ENDIAN _{Big-Endian DMA Mode Select.}
This bit should be set when using the DMA with big-endian multiple byte DMA trans-
fers. The DMA must also be configured for the same endian mode.
0 MODE _Mode.
0: Select Manchester encoding or decoding.
1:Select Three-out-of-Six encoding or decoding.
214
Rev. 1.0