C8051F960-B-GM Datasheet, PDF (469/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
(for n = 0 to 5)
PCA0CPMn
P ECCMT P E
WCAA AOWC
MOP P TGMC
1 MPN n n n F
6nnn
n
n
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
PCA Counter/Timer 16-
bit Overflow
PCA Module 0
(CCF0)
PCA0CN
CCCCCCCC
FRCCCCCC
FFFFFF
543210
PCA0MD
C WW C C C E
I DD PPPC
DT L SSSF
LEC 2 1 0
K
ECCF0
0
1
0
1
PCA Module 1
(CCF1)
ECCF1
0
1
PCA Module 2
(CCF2)
ECCF2
0
1
PCA Module 3
(CCF3)
ECCF3
0
1
PCA Module 4
(CCF4)
ECCF4
0
1
PCA Module 5
(CCF5)
ECCF5
0
1
PCA0PWM
A CE
CC
ROC
LL
S VO
SS
EFV
EE
L
LL
10
Set 8, 9, 10, or 11 bit Operation
0
1
EPCA0
EA
0
1
0 Interrupt
Priority
1 _Decoder
Figure 33.3. PCA Interrupt Block Diagram
33.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit
pulse width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-
51 system controller. These registers are used to exchange data with a module and configure the module's
mode of operation. Table 33.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM registers
used to select the PCA capture/compare module’s operating mode. Note that all modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
Table 33.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode
PCA0CPMn
PCA0PWM
Bit Number 7 6 5 4 3 2 1 0 7 6 5 4–2 1–0
Capture triggered by positive edge on CEXn
X X 1 0 0 0 0 A 0 X B XXX XX
Capture triggered by negative edge on CEXn
Capture triggered by any transition on CEXn
X X 0 1 0 0 0 A 0 X B XXX XX
X X 1 1 0 0 0 A 0 X B XXX XX
Rev. 1.0
469