C8051F960-B-GM Datasheet, PDF (330/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 25.16. PC0CMP1H: PC0 Comparator 1 High (MSB)
Bit
7
6
5
4
3
2
1
0
Name
PC0CMP1H[23:16]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF3; SFR Page = 0x2
Bit
Name
Function
7:0 PC0CMP1H[23:16] PC0 Comparator 1 High Byte
Bits 23:16 of Counter 0.
SFR Definition 25.17. PC0CMP1M: PC0 Comparator 1 Middle
Bit
7
6
5
4
3
2
1
0
Name
PC0CMP1M[15:8]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF2; SFR Page = 0x2
Bit
Name
Function
7:0 PC0CMP1M[15:8] PC0 Comparator 1 Middle Byte
Bits 15:8 of Counter 0.
SFR Definition 25.18. PC0CMP1L: PC0 Comparator 1 Low (LSB)
Bit
7
6
5
4
3
2
1
0
Name
PC0CMP1L[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF1; SFR Page = 0x2
Bit
Name
Function
7:0 PC0CMP1L[7:0] PC0 Comparator 1 Low Byte
Bits 7:0 of Counter 0.
Note: PC0CMP1L must be written last after writing PC0CMP1M and PC0CMP1H. After writing PC0CMP1L the
synchronization into the PC clock domain can take 2 RTC clock cycles.
330
Rev. 1.0