C8051F960-B-GM Datasheet, PDF (318/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
enable signal. The enable signal enables the pull-up resistor when high and disables when low. PC0 is the
line to the reed switch. On the right side of PC0 waveform, the line voltage is decreasing towards ground
when the pull-up resistors are disabled. Beneath the charging waveform, the arrows represent the sample
points. The pulse counter samples the PC0 voltage once the charging completes. The sensed ones and
zeros are the sampled data. Finally the integrator waveform illustrates the output of the digital integrator.
The integrator is set to 4 initially and counts to down to 0 before toggling the output low. Once the integra-
tor reaches the low state, it needs to count up to 4 before toggling its output to the high state. The
debounce logic filters out switch bounce or noise that appears for a short duration.
Debounce
Debounce
Switch
Charging
Samples
PC0
Sensed 1
1
0
1
1
0
0
0
0
1
0
1
1
1
1
Integrator
(set to 4)
Integrator 4
4
3
4
4
3
2
1
0
1
0
1
2
3
4
Integrator Output
Figure 25.4. Debounce Timing
25.7. Reset Behavior
Unlike most MCU peripherals, an MCU reset does not completely reset the Pulse Counter. This includes a
power on reset and all other reset sources. An MCU reset does not clear the counter values. The Pulse
Counter SFRs do not reset to a default value upon reset. The 24-bit counter values are persistent unless
cleared manually by writing to the PC0MD SFR. Note that if the VBAT voltage ever drops below the mini-
mum operating voltage, this may compromise contents of the counters.
The PC0MD register should normally be written only once after reset. The PC0MD SFR is the master
mode register. This register sets the counter mode and sample rate. Writing to the PC0MD SFR also
resets the other PC0xxx SFRs.
Note that the RTC clock will reset on an MCU reset, so counting cannot resume until the RTC clock has
been re-started.
Firmware should read the reset sources SFR RSTSRC to determine the source of the last reset and initial-
ize the Pulse Counter accordingly.
When the pulse counter resets, it takes some time (typically two RTC clock cycles) to synchronize between
internal clock domains. The counters do not increment during this synchronization time.
25.8. Wake up and Interrupt Sources
The Pulse Counter has multiple interrupt and wake-up source conditions. To enable an interrupt, enable
the source in the PC0INT0/1 SFRs and enable the Pulse Counter interrupt using bit 4 of the EIE2 bit regis-
ter. The Pulse Counter interrupt service routine should read the interrupt flags in PC0INT0/1 to determine
the source of the interrupt and clear the interrupt flags.
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Rev. 1.0