C8051F960-B-GM Datasheet, PDF (271/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
20.2. High Power Applications
The dc-dc converter is designed to provide the system with 150 mW of output power. At high output power,
an inductor with low dc resistance should be chosen in order to minimize power loss and maximize effi-
ciency. At load currents higher than 20 mA, efficiency improvents may be achieved by placing a schottky
diode (e.g. MBR052LT1) between the IND pin and GND in parallel with the internal diode (see
Figure 20.1).
20.3. Pulse Skipping Mode
The dc-dc converter allows the user to set the minimum pulse width such that if the duty cycle needs to
decrease below a certain width in order to maintain regulation, an entire "clock pulse" will be skipped.
Pulse skipping can provide substantial power savings, particularly at low values of load current. The con-
verter will continue to maintain a minimum output voltage at its programmed value when pulse skipping is
employed, though the output voltage ripple can be higher. Another consideration is that the dc-dc will oper-
ate with pulse-frequency modulation rather than pulse-width modulation, which makes the switching fre-
quency spectrum less predictable; this could be an issue if the dc-dc converter is used to power a radio.
20.4. Optimizing Board Layout
The PCB layout does have an effect on the overall efficiency. The following guidelines are recommended
to acheive the optimum layout:
 Place the input capacitor stack as close as possible to the VBATDC pin. The smallest capacitors in the
stack should be placed closest to the VBATDC pin.
 Place the output capacitor stack as close as possible to the VDC pin. The smallest capacitors in the
stack should be placed closest to the VDC pin.
 Minimize the trace length between the IND pin, the inductor, and the VDC pin.
20.5. Selecting the Optimum Switch Size
The dc-dc converter provides the ability to change the size of the built-in switches. To maximize efficiency,
one of two switch sizes may be selected. The large switches are ideal for carrying high currents and the
small switches are ideal for low current applications. The ideal switchover point to switch from the small
switches to the large switches is at approximately 5 mA total output current.
20.6. DC-DC Converter Clocking Options
The dc-dc converter may be clocked from its internal oscillator, or from any system clock source, select-
able by the CLKSEL bit (DC0CF.0). The dc-dc converter internal oscillator frequency is approximately
2.4 MHz. For a more accurate clock source, the system clock, or a divided version of the system clock may
be used as the dc-dc clock source. The dc-dc converter has a built in clock divider (configured using
DC0CF[6:5]) which allows any system clock frequency over 1.6 MHz to generate a valid clock in the range
of 1.9 to 3.8 MHz.
When the precision internal oscillator is selected as the system clock source, the OSCICL register may be
used to fine tune the oscillator frequency and the dc-dc converter clock. The oscillator frequency should
only be decreased since it is factory calibrated at its maximum frequency. The minimum frequency which
can be reached by the oscillator after taking into account process variations is approximately 16 MHz. The
system clock routed to the dc-dc converter clock divider also may be inverted by setting the CLKINV bit
(DC0CF.3) to logic 1. These options can be used to minimize interference in noise sensitive applications.
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