C8051F960-B-GM Datasheet, PDF (377/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 27.34. P5DRV: Port5 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
P5DRV[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA3
Bit
Name
Function
7:0 P5DRV[7:0] Drive Strength Configuration Bits for P5.7–P5.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P5.n Output has low output drive strength.
1: Corresponding P5.n Output has high output drive strength.
SFR Definition 27.35. P6: Port6
Bit
7
6
5
4
3
2
1
0
Name
P6[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address = 0xDB
Bit Name
Description
Write
Read
7:0 P6[7:0] Port 6 Data.
0: Set output latch to logic 0: P6.n Port pin is logic
Sets the Port latch logic
LOW.
LOW.
value or reads the Port pin ^{1: Set output latch to logic 1: P6.n Port pin is logic}
logic state in Port cells con- ^HIGH.
HIGH.
figured for digital I/O.
Rev. 1.0
377