C8051F960-B-GM Datasheet, PDF (338/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
26.3. LCD Contrast Adjustment
The LCD Bias voltages which determine the LCD contrast are generated using the VBAT supply voltage or
the on-chip charge pump. There are four contrast control modes to accomodate a wide variety of applica-
tions and supply voltages. The target contrast voltage is programmable in 60 mV steps from 1.9 to 3.72 V.
The LCD contrast voltage is controlled by the LCD0CNTRST register and the contrast control mode is
selected by setting the appropriate bits in the LCD0MSCN, LCD0MSCF, LCD0PWR, and LCD0VBMCN
registers.
Note: An external 10 µF decoupling capacitor is required on the VLCD pin to create a charge reservoir at the output of
the charge pump.
Table 26.1. Bit Configurations to select Contrast Control Modes
Mode
LCD0MSCN.2
LCD0MSCF.0
LCD0PWR.3
LCD0VBMCN.7
1
0
1
0
0
2
0
1
1
1
3
1*
0
1
1
4
1*
0
0
1
* May be set to 0 to support increased load currents.
26.3.1. Contrast Control Mode 1 (Bypass Mode)
In Contrast Control Mode 1, the contrast control circuitry is disabled and the VLCD voltage follows the
VBAT supply voltage, as shown in Figure 26.3. This mode is useful in systems where the VBAT voltage
always remains constant and will provide the lowest LCD power consumption. Bypass Mode is selected
using the following procedure:
1. Clear Bit 2 of the LCD0MSCN register to 0b (LCD0MSCN &= ~0x04)
2. Set Bit 0 of the LCD0MSCF register to 1b (LCD0MSCF |= 0x01)
3. Clear Bit 3 of the LCD0PWR register to 0b (LCD0PWR &= ~0x08)
4. Clear Bit 7 of the LCD0VBMCN register to 0b (LCD0VBMCN &= ~0x80)
VBAT
VLCD
Figure 26.3. Contrast Control Mode 1
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Rev. 1.0