C8051F960-B-GM Datasheet, PDF (155/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 11.6. DMA0NMD: DMA Channel Mode
Bit
7
6
5
4
3
2
1
0
Name
WRAP
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xD6
Bit
Name
Function
7:1
reserved
Read = 0, Write = 0
0
WRAP
Wrap Enable.
Setting this bit will enable wrapping.
The DMA0NSZ register sets the transfer size. Normally the DMA0AO value
starts at zero in increases to the DMANSZ minus one. At this point the trans-
fer is complete and the interrupt bit will be set. If the WRAP bit is set, the
DMA0NAO will be reset to zero.
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
Rev. 1.0
155