C8051F960-B-GM Datasheet, PDF (154/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 11.5. DMA0SEL: DMA0 Channel Select for Configuration
Bit
7
Name
Type
R
Reset
0
6
5
4
3
R/W
R/W
R/W
R/W
0
0
0
0
2
1
0
DMA0SEL[2:0]
R/W
0
0
0
SFR Page = 0x2; SFR Address = 0xD1
Bit
Name
Function
7:3
Unused
Read = 0b, Write = Don’t Care
2:0 DMA0SEL[2:0] Channel Select for Configuration.
These bits select the channel for configuration of the DMA0 transfer. The
first step to configure a channel for DMA0 transfer is to select the desired
channel, and then write to channel specific registers DMA0NCF,
DMA0NBAL/H, DMA0NAOL/H, DMA0NSZL/H.
000: Select channel 0
001: Select channel 1
010: Select channel 2
011: Select channel 3
100: Select channel 4
101: Select channel 5
110: Select channel 6
111: Invalid
154
Rev. 1.0