C8051F960-B-GM Datasheet, PDF (85/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
5.5. Low Power Mode
The SAR converter provides a low power mode that allows a significant reduction in operating current
when operating at low SAR clock frequencies. Low power mode is enabled by setting the AD0LPM bit
(ADC0PWR.7) to 1. In general, low power mode is recommended when operating with SAR conversion
clock frequency at 4 MHz or less. See the Electrical Characteristics chapter for details on power consump-
tion and the maximum clock frequencies allowed in each mode. Setting the Low Power Mode bit reduces
the bias currents in both the SAR converter and in the High-Speed Voltage Reference.
Table 5.1. Representative Conversion Times and Energy Consumption for the SAR ADC
with 1.65 V High-Speed VREF
Normal Power Mode
Low Power Mode
8 bit
10 bit
12 bit
8 bit
10 bit
12 bit
Highest nominal
SAR clock
frequency
8.17 MHz 8.17 MHz
(24.5/3)
(24.5/3)
6.67 MHz
(20.0/3)
4.08
MHz
(24.5/6)
4.08
MHz
(24.5/6)
4.00 MHz
(20.0/5)
Total number of
11
conversion clocks
required
13
52 (13 x 4)
11
13
52 (13*4)
Total tracking time
(min)
1.5 µs
1.5 µs
4.8 µs
(1.5+3 x 1.1)
1.5 µs
1.5 µs
4.8 µs
(1.5+3 x 1.1)
Total time for one
conversion
2.85 µs
3.09 µs
12.6 µs
4.19 µs 4.68 µs
17.8 µs
ADC Throughput 351 ksps 323 ksps
79 ksps 238 ksps 214 ksps 56 ksps
Energy per
conversion
8.2 nJ
8.9 nJ
36.5 nJ
6.5 nJ 7.3 nJ
27.7 nJ
Note: This table assumes that the 24.5 MHz precision oscillator is used for 8- and 10-bit modes, and the 20 MHz
low power oscillator is used for 12-bit mode. The values in the table assume that the oscillators run at their
nominal frequencies. The maximum SAR clock values given in Table 4.12 allow for maximum oscillation
frequencies of 25.0 MHz and 22 MHz for the precision and low-power oscillators, respectively, when using
the given SAR clock divider values. Energy calculations are for the ADC subsystem only and do not include
CPU current.
Rev. 1.0
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