C8051F960-B-GM Datasheet, PDF (68/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 4.6. Reset Electrical Characteristics
V_BAT = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified.
Parameter
RST Output Low Voltage
RST Input High Voltage
Conditions
I_OL = 1.4 mA,
V_BAT = 2.0 to 3.8 V
Min Typ
—
—
V_BAT – _—
0.6
Max
0.6
—
V_BAT = 1.8 to 2.0 V
RST Input Low Voltage
V_BAT = 2.0 to 3.8 V
V_BAT = 1.8 to 2.0 V
RST Input Pullup Current
VBAT Monitor Threshold
(V_RST)*
VBAT Ramp Time for
Power On*
POR Monitor Threshold
(V_POR)
Missing Clock Detector
Timeout
RST = 0.0 V, V_BAT = 1.8 V
RST = 0.0 V, V_BAT = 3.8 V
Early Warning
Reset Trigger
(all power modes except Sleep)
VBAT Ramp from 0–1.8 V
Brownout Condition (V_BAT Falling)
Recovery from Brownout (V_BAT Rising)
Time from last system clock rising edge
to reset initiation
0.7 x
V_BAT
—
—
—
—
1.8
1.7
—
0.45
—
100
—
—
—
4
20
1.85
1.75
—
0.7
1.75
650
—
0.6
0.3 x
V_BAT
—
35
1.9
1.8
3
1.0
—
1000
Minimum System Clock w/
Missing Clock Detector
Enabled
System clock frequency which triggers
a missing clock detector timeout
—
7
10
Reset Time Delay
Delay between release of any reset
source and code
execution at location 0x0000
—
10
—
Minimum RST Low Time to
Generate a System Reset
15
—
—
Digital/Analog Monitor
Turn-on Time
Digital Monitor Supply 
Current
—
300
—
—
14
—
Analog Monitor Supply 
Current
—
14
—
*Note: The VBAT monitor electical specifications apply to both the analog and digital VBAT monitors (“SFR
Definition 22.1. VDM0CN: VDD Supply Monitor Control” on page 282).
Units
V
V
V
V
V
µA
V
ms
V
µs
kHz
µs
µs
ns
µA
µA
68
Rev. 1.0