C8051F960-B-GM Datasheet, PDF (262/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 19.3. CLKMODE: Clock Mode
Bit
7
6
5
4
3
2
1
0
Name Reserved Reserved Reserved Reserved Reserved LPMEN Reserved Reserved
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xFD; Bit-Addressable
Bit
Name
Function
7:3
Reserved Read = 0b; Write = Must write 00000b.
2
LPMEN
Low Power Mode Enable.
Setting this bit allows the device to enter Low Power Active or Idle Mode.
1
Reserved Read = 0b; Must write 0b.
0
Reserved Read = 0b; Must write 0b.
262
Rev. 1.0