C8051F960-B-GM Datasheet, PDF (429/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
31.3. SPI1 Slave Mode Operation
When SPI1 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK
signal. A bit counter in the SPI1 logic counts SCK edges. When 8 bits have been shifted through the shift
register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI1DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI1DAT. Writes to SPI1DAT are double-
buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI1 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI1CN.3) = 0 and NSSMD0 (SPI1CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI1 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS
signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte
transfer. Figure 31.4 shows a connection diagram between two slave devices in 4-wire slave mode and a
master device.
3-wire slave mode is active when NSSMD1 (SPI1CN.3) = 0 and NSSMD0 (SPI1CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI1 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI1 with the SPIEN bit. Figure 31.3 shows a connection diagram between a slave device in 3-
wire slave mode and a master device.
31.4. SPI1 Interrupt Sources
When SPI1 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
 The SPI Interrupt Flag, SPIF (SPI1CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI1 modes.
 The Write Collision Flag, WCOL (SPI1CN.6) is set to logic 1 if a write to SPI1DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI1DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI1
modes.
 The Mode Fault Flag MODF (SPI1CN.5) is set to logic 1 when SPI1 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI1CN are set to logic 0 to disable SPI1 and allow another master device to access the bus.
 The Receive Overrun Flag RXOVRN (SPI1CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
Rev. 1.0
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