C8051F960-B-GM Datasheet, PDF (343/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 26.5. LCD0MSCF: LCD0 Master Configuration
Bit
7
6
Name
Type ^R/W
R/W
Reset
1
1
5
R/W
1
4
3
2
1
0
DCENSLP CHPBYP
R/W
R/W
R/W
R/W
R/W
1
1
1
1
0
SFR Page = 0x2; SFR Address = 0xAC
Bit
Name
Function
7:2 Reserved Read = 111111b. Must write 111111b.
1 DCENSLP _{DCDC Converter Enable in Sleep Mode}
0: DCDC is disabled in Sleep Mode.
1: DCDC is enabled in Sleep Mode.
0
CHPBYP LCD0 Charge Pump Bypass
This bit should be set to 1b in Contrast Control Mode 1 and Mode 2.
0: LCD0 Charge Pump is not bypassed.
1: LCD0 Charge Pump is bypassed.
SFR Definition 26.6. LCD0PWR: LCD0 Power
Bit
7
6
Name
Type ^R/W
R/W
Reset
0
0
5
R/W
0
4
3
2
1
0
MODE
R/W
R/W
R/W
R/W
R/W
0
1
0
0
1
SFR Page = 0x2; SFR Address = 0xA4
Bit
Name
Function
7:4 Unused Read = 0000b. Write = don’t care.
3
MODE LCD0 Contrast Control Mode Selection.
0: LCD0 Contrast Control Mode 1 or Mode 4 is selected.
1: LCD0 Contrast Control Mode 2 or Mode 3 is selected.
2:0 Reserved Read = 001b. Must write 001b.
Rev. 1.0
343