C8051F960-B-GM Datasheet, PDF (191/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
14.6.1.1. CBC Encryption Data Flow
The AES0 module data flow for CBC encryption is shown in Figure 14.5. The plaintext is written to the
AES0BIN sfr. For the first block, the initialization vector is written to the AES0XIN sfr. For subsequent
blocks, the previous block ciphertext is written to the AES0XIN sfr. The AES0DCF sfr is configured to XOR
AES0XIN with AES0BIN for the AES core data input. The XOR on the output is not used. The AES core is
configured for an encryption operation. The encryption key is written to AES0KIN. The key size is set to the
desired key size.
internal state
machine
AES0BIN
+
AES0XIN
AES0DCFG
AES0KIN
Data In
Key
AES
Key
In
Core
Out
Data Out
AES0BCFG
+
AES0YOUT
Figure 14.5. CBC Encryption Data Flow
Rev. 1.0
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