C8051F960-B-GM Datasheet, PDF (280/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
22.2. Power-Fail Reset
C8051F96x devices have two Active Mode Supply Monitors that can hold the system in reset if the supply
voltage drops below V_RST. The first of the two identical supply monitors is connected to the output of the
supply select switch (which chooses the VBAT or VDC pin as the source of the digital supply voltage) and
is enabled and selected as a reset source after each power-on or power-fail reset. This supply monitor will
be referred to as the digital supply monitor. The second supply monitor is connected directly to the VBAT
pin and is disabled after each power-on or power-fail reset. This supply monitor will be referred to as the
analog supply monitor. The analog supply monitor should be enabled any time the supply select switch is
set to the VDC pin to ensure that the VBAT supply does not drop below V_RST .
When enabled and selected as a reset source, any power down transition or power irregularity that causes
the monitored supply voltage to drop below V_RST will cause the RST pin to be driven low and the CIP-51
will be held in a reset state (see Figure 22.2). When the supply voltage returns to a level above V_RST, the
CIP-51 will be released from the reset state.
After a power-fail reset, the PORSF flag reads 1, the contents of RAM are invalid, and the digital supply
monitor is enabled and selected as a reset source. The enable state of either supply monitor and its selec-
tion as a reset source is only altered by power-on and power-fail resets. For example, if the supply monitor
is de-selected as a reset source and disabled by software, then a software reset is performed, the supply
monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in Sleep Mode prior to a power-fail reset occurring. When the device is in Sleep
Mode, the power-fail reset is automatically disabled, both active mode supply monitors are turned off, and
the contents of RAM are preserved as long as the supply does not fall below V_POR. A large capacitor can
be used to hold the power supply voltage above V_POR while the user is replacing the battery. Upon waking
from Sleep mode, the enable and reset source select state of the V_DD supply monitor are restored to the
value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the supply falls below the V_WARN threshold. The VDDOK bit can be configured to generate an interrupt.
Each of the active mode supply montiors have their independent VDDOK and V_WARN flags. See Section
“17. Interrupt Handler” on page 232 for more details.
Important Note: To protect the integrity of Flash contents, the active mode supply monitor(s) must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the digital supply monitor is not enabled, any erase or write performed on Flash memory will
cause a Flash Error device reset.
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