C8051F960-B-GM Datasheet, PDF (226/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
ENC0H
0xC4
0x2 _{ENC0 High}
ENC0L
0xC2
0x2 ENC0 Low
ENC0M
0xC3
0x2 _{ENC0 Middle}
FLKEY
0xB7 All Pages _{Flash Lock And Key}
FLSCL
0xB6
0xF Flash Scale Register
FLWR
0xE5
0x0 _{Flash Write Only}
FRBCN
0xB5
0xF _{Flash Read Buffer Control}
IE
0xA8 All Pages Interrupt Enable
IP
0xB8 All Pages _{Interrupt Priority}
IREF0CF
0xB9
0xF _{Current Reference IREF0 Configuration}
IREF0CN
0xB9
0x0 Current Reference IREF0 Configuration
IT01CF
0xE4
0x0 and _{INT0/INT1 Configuration}
0xF
LCD0BLINK
0x9E
0x2 _{LCD0 Blink Mask}
LCD0BUFCF
0xAC
0xF _{LCD0 Buffer Configuration}
LCD0BUFCN
0x9C
0xF LCD0 Buffer Control
LCD0BUFMD 0xB6
0x2 _{LCD0 Buffer Mode}
LCD0CF
0xA5
0x2 _{LCD0 Configuration}
LCD0CHPCF 0xAD
0x2 LCD0 Charge Pump Configuration
LCD0CHPCN 0xB5
0x2 _{LCD0 Charge Pump Control}
LCD0CHPMD 0xAE
0x2 _{LCD0 Charge Pump Mode}
LCD0CLKDIVH 0xAA
0x2 _{LCD0 Clock Divider High}
LCD0CLKDIVL 0xA9
0x2 _{LCD0 Clock Divider Low}
LCD0CN
0x9D
0x2 LCD0 Control
LCD0CNTRST 0x9C
0x2 _{LCD0 Contrast}
LCD0D0
0x89
0x2 _{LCD0 Data 0}
LCD0D1
0x8A
0x2 LCD0 Data 1
LCD0D2
0x8B
0x2 _{LCD0 Data 2}
LCD0D3
0x8C
0x2 _{LCD0 Data 3}
LCD0D4
0x8D
0x2 LCD0 Data 4
LCD0D5
0x8E
0x2 _{LCD0 Data 5}
LCD0D6
0x91
0x2 _{LCD0 Data 6}
LCD0D7
0x92
0x2 LCD0 Data 7
LCD0D8
0x93
0x2 _{LCD0 Data 8}
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