C8051F960-B-GM Datasheet, PDF (310/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Internal Register Definition 24.8. CAPTUREn: SmaRTClock Timer Capture
Bit
7
6
5
4
3
2
1
0
Name
CAPTURE[31:0]
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SmaRTClock Addresses: CAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPTURE2 =0x02; CAPTURE3: 0x03.
Bit
Name
Function
7:0 CAPTURE[31:0] SmaRTClock Timer Capture.
These 4 registers (CAPTURE3–CAPTURE0) are used to read or set the 32-bit
SmaRTClock timer. Data is transferred to or from the SmaRTClock timer when
the RTC0SET or RTC0CAP bits are set.
Note: The least significant bit of the timer capture value is CAPTURE0.0.
Internal Register Definition 24.9. ALARM0Bn: SmaRTClock Alarm 0 Match Value
Bit
7
6
5
4
3
2
1
0
Name
ALARM0[31:0]
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SmaRTClock Address: ALARM0B0 = 0x08; ALARM0B1 = 0x09; ALARM0B2 = 0x0A; ALARM0B3 = 0x0B
Bit
Name
Function
7:0 ALARM0[31:0] SmaRTClock Alarm 0 Programmed Value.
These 4 registers (ALARM0B3–ALARM0B0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (ALRM0EN=0)
when updating these registers.
Note: The least significant bit of the alarm programmed value is ALARM0B0.0.
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Rev. 1.0