C8051F960-B-GM Datasheet, PDF (225/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
CRC1CN
0xBE
0x2 _{CRC1 Control}
CRC1IN
0xB9
0x2 CRC1 In
CRC1OUTH
0xBB
0x2 _{CRC1 Out High}
CRC1OUTL
0xBA
0x2 _{CRC1 Out Low}
CRC1POLH
0xBD
0x2 CRC1 Polynomial High
CRC1POLL
0xBC
0x2 _{CRC1 Polynomial Low}
DC0CF
0xB2
0x2 _{DC0 Configuration}
DC0CN
0xB1
0x2 DC0 Control
DC0MD
0xB3
0x2 _{DC0 Mode}
DC0RDY
0xFD
0x2 _{DC0 Ready}
DEVICEID
0xE9
0xF Device ID
DMA0BUSY
0xD5
0x2 _{DMA0 Busy}
DMA0EN
0xD2
0x2 _{DMA0 Enable}
DMA0INT
0xD3
0x2 DMA0 Interrupt
DMA0MINT
0xD4
0x2 _{DMA0 Middle Interrupt}
DMA0NAOH
0xCD
0x2 _{DMA0 Address Offset High (Selected Channel)}
DMA0NAOL
0xCC
0x2 DMA0 Address Offset Low (Selected Channel)
DMA0NBAH
0xCB
0x2 _{DMA0 Base Address High (Selected Channel)}
DMA0NBAL
0xCA
0x2 _{DMA0 Base Address Low (Selected Channel)}
DMA0NCF
0xC9
0x2 DMA0 Configuration
DMA0NMD
0xD6
0x2 _{DMA0 Mode (Selected Channel)}
DMA0NSZH
0xCF
0x2 DMA0 Size High (Selected Channel)
DMA0NSZL
0xCE
0x2 _{DMA0 Size Low (Selected Channel)}
DMA0SEL
0xD1
0x2 _{DMA0 Channel Select}
DPH
0x83 All Pages Data Pointer High
DPL
0x82 All Pages _{Data Pointer Low}
EIE1
0xE6 All Pages _{Extended Interrupt Enable 1}
EIE2
0xE7 All Pages Extended Interrupt Enable 2
EIP1
0xF6 All Pages _{Extended Interrupt Priority 1}
EIP2
0xF7 All Pages _{Extended Interrupt Priority 2}
EMI0CF
0xAB
0x0 EMIF Configuration
EMI0CN
0xAA
0x0 _{EMIF Control}
EMI0TC
0xAF
0x0 _{EMIF Timing Control}
ENC0CN
0xC5
0x2 ENC0 Control
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Rev. 1.0
225