C8051F960-B-GM Datasheet, PDF (369/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 27.18. P2: Port2
Bit
7
6
5
4
3
2
1
0
Name
P2[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0xA0; Bit-Addressable
Bit Name
Description
Write
Read
7:0 P2[7:0] Port 2 Data.
0: Set output latch to logic 0: P2.n Port pin is logic
Sets the Port latch logic
LOW.
LOW.
value or reads the Port pin ^{1: Set output latch to logic 1: P2.n Port pin is logic}
logic state in Port cells con- ^HIGH.
HIGH.
figured for digital I/O.
SFR Definition 27.19. P2SKIP: Port2 Skip
Bit
7
6
5
4
3
2
1
0
Name
P2SKIP[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xD6
Bit
Name
Function
7:0 P2SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
Rev. 1.0
369