C8051F960-B-GM Datasheet, PDF (197/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
14.6.4.2. CBC Decryption using SFRs
 First Configure AES Module for CBC Block Cipher Mode Decryption
Reset AES module by writing 0x00 to AES0BCFG.
Configure the AES Module data flow for XOR on output data by writing 0x02 to the AES0DCFG sfr.
Write key size to bits 1 and 0 of the AES0BCFG.
Configure the AES core for decryption by setting bit 2 of AES0BCFG.
Enable the AES core by setting bit 3 of AES0BCFG.
 Repeat alternating write sequence 16 times
Write plaintext byte to AES0BIN.
Write encryption key byte to AES0KIN.
 Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit decryption only.
 Wait on AES done interrupt or poll bit 5 of AES0BCFG.
 Repeat alternating write read sequence 16 times
Write initialization vector to AES0XIN
Read decrypted data from AES0YOUT
If decrypting multiple blocks, this process may be repeated. It is not necessary reconfigure the AES mod-
ule for each block. When using Cipher Block Chaining the initialization vector is written to the AES0XIN sfr
for the first block only, as described. Additional blocks will chain the ciphertext data from the previous
block.
Rev. 1.0
197