C8051F960-B-GM Datasheet, PDF (337/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 26.2. LCD0CN: LCD0 Control Register
Bit
7
Name
Type
R/W
Reset
0
6
5
CLKDIV[1:0]
R/W
R/W
0
0
4
BLANK
R/W
0
3
SIZE
R/W
0
2
1
MUXMD[1:0]
R/W
0
0
0
BIAS
R/W
0
SFR Page = 0x2; SFR Address = 0x9D
Bit
Name
Function
7
Reserved Read = 0. Must Write 0b.
6:5 CLKDIV[1:0] _{LCD0 Clock Divider.}
Divides the SmaRTClock output for use by the LCD0 module. See Table 4.18 on
page 76 for LCD clock frequency range.
00: The LCD clock is the SmaRTClock divided by 1.
01: The LCD clock is the SmaRTClock divided by 2.
10: The LCD clock is the SmaRTClock divded by 4.
11: Reserved.
4
BLANK _{Blank All Segments.}
Blanks all LCD segments using a single bit.
0: All LCD segments are controlled by the LCD0Dn registers.
1: All LCD segments are blank (turned off).
3
SIZE
LCD Size Select.
Selects whether 16 or 32 segment pins will be used for the LCD function.
0: P0 and P1 are used as LCD segment pins.
1: P0, P1, P2, and P3 are used as LCD segment pins.
2:1 MUXMD[1:0] _{LCD Bias Power Mode.}
Selects the mux mode.
00: Static mode selected.
01: 2-mux mode selected.
10: 3-mux mode selected.
11: 4-mux mode selected.
0
BIAS
Bias Select.
Selects between 1/2 Bias and 1/3 Bias. This bit is ignored if Static mode is
selected.
0: LCD0 is configured for 1/3 Bias.
1: LCD0 is configured for 1/2 Bias.
Rev. 1.0
337