C8051F960-B-GM Datasheet, PDF (323/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 25.3. PC0TH: PC0 Threshold Configuration
Bit
Name
7
6
PCTTHRESHI[1:0]
5
4
3
2
PCTHRESLO[1:0] PDOWN PUP
1
0
RDVALID
Type
R/W
R/W
R/W
R/W
R
R/W
Reset
0
0
0
0
0
0
0
1
SFR Address = 0xE4; SFR Page = 0x2
Bit
Name
Function
7:6 PCTTHRESHI[1:0] Pulse Counter Input Comparator VIH Threshold
(Percentage of VIO.)
10: 50%
11: 55%
00: 59%
01: 63%
5:4 PCTHRESLO[1:0] Pulse Counter Input Comparator VIL Threshold
(percentage of VIO.)
10: 34%
11: 38%
00: 42%
01: 46%
3
PDOWN
Force Pull-Down On
0: PC0 and PC1 pull-down not forced on.
1: PC0 and PC1 grounded.
2
PUP
Force Pull-Up
0: PC0 and PC1 pull-up not forced on continuously. See PC0PCF[1:0] for
duty cycle.
1: PC0 and PC1 pulled high continuously to the PC0PCF[4:2] setting.
PDOWN overrides PUP setting.
1
Reserved
0
RDVALID
Read Valid
Holds the status of the last read for real-time registers PC0STAT, PC0HIST,
PC0CTR0L, PC0CTR1L, PC0INT0, and PC0INT1.
0: The last read was invalid.
1: The last read was valid.
RDVALID is set back to 1 upon reading.
Rev. 1.0
323