C8051F960-B-GM Datasheet, PDF (166/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 12.4. CRC0AUTO: CRC0 Automatic Control
Bit
7
6
5
4
Name ^{AUTOEN CRCDONE}
Type
R/W
Reset
0
1
0
0
3
2
CRC0ST[5:0]
0
0
1
0
R/W
0
0
SFR Page = 0xF; SFR Address = 0x96
Bit
Name
Function
7
AUTOEN Automatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at flash sector CRC0ST and continuing for CRC0CNT sectors.
6 CRCDONE CRCDONE Automatic CRC Calculation Complete.
Set to 0 when a CRC calculation is in progress. Note that code execution is
stopped during a CRC calculation, therefore reads from firmware will always
return 1.
5:0 CRC0ST[5:0] Automatic CRC Calculation Starting Flash Sector.
These bits specify the flash sector to start the automatic CRC calculation. The
starting address of the first flash sector included in the automatic CRC calculation
is CRC0ST x 1024. For 128 kB devices, pages 32–63 access the upper code
bank as selected by the IFBANK bits in the PSBANK SFR.
SFR Definition 12.5. CRC0CNT: CRC0 Automatic Flash Sector Count
Bit
7
6
5
4
3
2
1
0
Name
CRC0CNT[5:0]
Type
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x97
Bit
Name
Function
7:6
Unused Read = 00b; Write = Don’t Care.
5:0 CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
These bits specify the number of flash sectors to include in an automatic CRC cal-
culation. The starting address of the last flash sector included in the automatic
CRC calculation is (CRC0ST+CRC0CNT) x 1024. The last page should not
exceed page 63. Setting both CRC0ST and CRC0CNT to 0 will perform a CRC
over the 64kB banked memory space.
166
Rev. 1.0