C8051F960-B-GM Datasheet, PDF (361/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
27.4. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMAT registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMAT registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(PnMAT & P0MASK) or if (P1 & P1MASK) does not equal (PnMAT & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode.
See Section “17. Interrupt Handler” on page 232 and Section “19. Power Management” on page 257 for
more details on interrupt and wake-up sources.
SFR Definition 27.4. P0MASK: Port0 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
P0MASK[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xC7
Bit
Name
Function
7:0 P0MASK[7:0] Port0 Mask Value.
Selects the P0 pins to be compared with the corresponding bits in P0MAT.
0: P0.n pin pad logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin pad logic value is compared to P0MAT.n.
SFR Definition 27.5. P0MAT: Port0 Match Register
Bit
7
6
5
4
3
2
1
0
Name
P0MAT[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page= 0x0; SFR Address = 0xD7
Bit
Name
Function
7:0 P0MAT[7:0] Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
Rev. 1.0
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