C8051F960-B-GM Datasheet, PDF (227/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
LCD0D9
0x94
0x2 _{LCD0 Data 9}
LCD0DA
0x95
0x2 LCD0 Data A
LCD0DB
0x96
0x2 _{LCD0 Data B}
LCD0DC
0x97
0x2 _{LCD0 Data C}
LCD0DD
0x99
0x2 LCD0 Data D
LCD0DE
0x9A
0x2 _{LCD0 Data E}
LCD0DF
0x9B
0x2 _{LCD0 Data F}
LCD0MSCF
0xAC
0x2 LCD0 Master Configuration
LCD0MSCN
0xAB
0x2 _{LCD0 Master Control}
LCD0PWR
0xA4
0x2 _{LCD0 Power}
LCD0TOGR
0x9F
0x2 LCD0 Toggle Rate
LCD0VBMCF 0xAF
0x2 _{LCD0 VBAT Monitor Configuration}
LCD0VBMCN 0xA6
0x2 _{LCD0 VBAT Monitor Control}
OSCICL
0xB3
0xF Internal Oscillator Calibration
OSCICN
0xB2
0x0 _{Internal Oscillator Control}
OSCXCN
0xB1
0x0 _{External Oscillator Control}
P0DRV
0xA4
0xF Port 0 Drive Strength
P0MASK
0xC7
0x0 _{Port 0 Mask}
P0MAT
0xD7
0x0 _{Port 0 Match}
P0MDIN
0xF1
0x0 Port 0 Input Mode Configuration
P0MDOUT
0xA4
0x0 _{Port 0 Output Mode Configuration}
P0SKIP
0xD4
0x0 Port 0 Skip
P0
0x80 All Pages _{Port 0 Latch}
P1DRV
0xA5
0xF _{Port 1 Drive Strength}
P1MASK
0xBF
0x0 Port 1 Mask
P1MAT
0xCF
0x0 _{Port 1 Match}
P1MDIN
0xF2
0x0 _{Port 1 Input Mode Configuration}
P1MDOUT
0xA5
0x0 Port 1 Output Mode Configuration
P1SKIP
0xD5
0x0 _{Port 1 Skip}
P1
0x90 All Pages _{Port 1 Latch}
P2DRV
0xA6
0xF Port 2 Drive Strength
P2MDIN
0xF3
0x0 _{Port 2 Input Mode Configuration}
P2MDOUT
0xA6
0x0 _{Port 2 Output Mode Configuration}
P2SKIP
0xD6
0x0 Port 2 Skip
Page
335
335
335
335
335
335
335
343
342
343
347
350
344
293
292
294
366
361
361
365
365
364
364
368
362
362
367
368
367
366
371
370
370
369
Rev. 1.0
227