C8051F960-B-GM Datasheet, PDF (12/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Figure 26.1. LCD Segment Driver Block Diagram ................................................. 334
Figure 26.2. LCD Data Register to LCD Pin Mapping ........................................... 336
Figure 26.3. Contrast Control Mode 1 ................................................................... 338
Figure 26.4. Contrast Control Mode 2 ................................................................... 339
Figure 26.5. Contrast Control Mode 3 ................................................................... 339
Figure 26.6. Contrast Control Mode 4 ................................................................... 340
Figure 27.1. Port I/O Functional Block Diagram .................................................... 351
Figure 27.2. Port I/O Cell Block Diagram .............................................................. 352
Figure 27.3. Crossbar Priority Decoder with No Pins Skipped .............................. 356
Figure 27.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 357
Figure 28.1. SMBus Block Diagram ...................................................................... 381
Figure 28.2. Typical SMBus Configuration ............................................................ 382
Figure 28.3. SMBus Transaction ........................................................................... 383
Figure 28.4. Typical SMBus SCL Generation ........................................................ 385
Figure 28.5. Typical Master Write Sequence ........................................................ 394
Figure 28.6. Typical Master Read Sequence ........................................................ 395
Figure 28.7. Typical Slave Write Sequence .......................................................... 396
Figure 28.8. Typical Slave Read Sequence .......................................................... 397
Figure 29.1. UART0 Block Diagram ...................................................................... 402
Figure 29.2. UART0 Baud Rate Logic ................................................................... 403
Figure 29.3. UART Interconnect Diagram ............................................................. 404
Figure 29.4. 8-Bit UART Timing Diagram .............................................................. 404
Figure 29.5. 9-Bit UART Timing Diagram .............................................................. 405
Figure 29.6. UART Multi-Processor Mode Interconnect Diagram ......................... 406
Figure 30.1. SPI Block Diagram ............................................................................ 411
Figure 30.2. Multiple-Master Mode Connection Diagram ...................................... 414
Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave Mode 
Connection Diagram ......................................................................... 414
Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave Mode 
Connection Diagram ......................................................................... 414
Figure 30.5. Master Mode Data/Clock Timing ....................................................... 416
Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 416
Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 417
Figure 30.8. SPI Master Timing (CKPHA = 0) ....................................................... 421
Figure 30.9. SPI Master Timing (CKPHA = 1) ....................................................... 421
Figure 30.10. SPI Slave Timing (CKPHA = 0) ....................................................... 422
Figure 30.11. SPI Slave Timing (CKPHA = 1) ....................................................... 422
Figure 32.1. T0 Mode 0 Block Diagram ................................................................. 447
Figure 32.2. T0 Mode 2 Block Diagram ................................................................. 448
Figure 32.3. T0 Mode 3 Block Diagram ................................................................. 449
Figure 32.4. Timer 2 16-Bit Mode Block Diagram ................................................. 454
Figure 32.5. Timer 2 8-Bit Mode Block Diagram ................................................... 455
Figure 32.6. Timer 2 Capture Mode Block Diagram .............................................. 456
Figure 32.7. Timer 3 16-Bit Mode Block Diagram ................................................. 460
Figure 32.8. Timer 3 8-Bit Mode Block Diagram ................................................... 461
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Rev. 1.0