C8051F960-B-GM Datasheet, PDF (217/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFRPGCN Bit
Interrupt
Logic
CIP-51
SFRPAGE
SFRNEXT
SFRLAST
Figure 16.1. SFR Page Stack
Automatic hardware preserving and restoring of the SFR Page on interrupts may be enabled or disabled
as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register
(SFR0CN). This function defaults to “enabled” upon reset. In this way, the autoswitching function will be
enabled unless disabled in software.
A summary of the SFR locations (address and SFR page) are provided in Table 16.3 in the form of an SFR
memory map. Each memory location in the map has an SFR page row, denoting the page in which that
SFR resides. Certain SFRs are accessible from ALL SFR pages, and are denoted by the “(ALL PAGES)”
designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “(ALL PAGES)” designa-
tion, indicating these SFRs are accessible from all SFR pages regardless of the SFRPAGE register value.
Rev. 1.0
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