C8051F960-B-GM Datasheet, PDF (159/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 11.12. DMA0NSZH: Transfer Size High Byte
Bit
7
6
5
4
3
2
1
0
Name
NSZH[1:0]
Type
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xCF
Bit
Name
Function
7:2
Unused
Read = 0b, Write = Don’t Care
1:0
NSZH[1:0]
Transfer Size High Byte.
Sets high byte of DMA0 transfer size of the selected channel. Transfer size
sets the maximum number of bytes for the DMA0 transfer. When the
address offset is equal to the transfer size, a full-length interrupt is gener-
ated on the channel.
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
SFR Definition 11.13. DMA0NSZL: Memory Transfer Size Low Byte
Bit
7
6
5
4
3
2
1
0
Name
NSZL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xCE
Bit
Name
Function
7:0
NSZL[7:0]
Memory Transfer Size Low Byte.
Sets low byte of DMA0 transfer size of the selected channel. Transfer size
sets the maximum number of bytes for the DMA0 transfer. When the
address offset is equal to the transfer size, a full-length interrupt is gener-
ated on the channel.
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
Rev. 1.0
159