C8051F960-B-GM Datasheet, PDF (213/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
15.7. Using the ENC0 module with the DMA
The steps for Encoding/Decoding using the DMA are as follows.
1. Clear the ENC module by writing 0x00 to the ENC0CN SFR.
2. Configure the first DMA channel for the XRAM-to-ENC0 input transfer:
a. Disable the first DMA channel by clearing the corresponding bit in DMA0EN.
b. Select the first DMA channel by writing to DMA0SEL.
c. Configure the selected DMA channel to use the XRAM-to-ENC0 input peripheral request by
writing 0x00 to DMA0NCF.
d. Set the ENDIAN bit in DMA0NCF to enable big-endian multi-byte DMA transfers.
e. Write 0 to DMA0NMD to disable wrapping.
f. Write the address of the first byte of input data DMA0NBAH:L.
g. Write the size of the input data transfer in bytes to DMA0NSZH:L.
h. Clear the address offset SFRs DMA0A0H:L.
3. Configure the second DMA channel for the ENC0-to-XRAM output transfer:
a. Disable the second DMA channel by clearing the corresponding bit in DMA0EN.
b. Select the second DMA channel by writing to DMA0SEL.
c. Configure the selected DMA channel to use the SPI1DAT-to-XRAM output peripheral request by
writing 0x01 to DMA0NCF.
d. Set the ENDIAN bit in DMA0NCF to enable big-endian multi-byte DMA transfers.
e. Enable DMA interrupts for the second channel by setting bit 7 of DMA0NCF.
f. Write 0 to DMA0NMD to disable wrapping.
g. Write the address for the first byte of the output data to DMA0NBAH:L.
h. Write the size of the output data transfer in bytes to DMA0NSZH:L.
i. Clear the address offset SFRs DMA0A0H:L.
j. Enable the interrupt on the second channel by setting the corresponding bit in DMA0INT.
4. Clear the interrupt bits in DMA0INT for both channels.
5. Enable DMA interrupts by setting bit 5 of EIE2.
6. If desired for a decode operation, enable the ERROR interrupt bit by setting bit 6 of EIE2.
7. Write the operation value to ENC0CN setting ENC, DEC, and MODE bits for the desired operation.
The DMA bit and ENDIAN bits must be set. The READY bits and ERROR bits must be cleared.
a. Write 0x16 for Manchester Decode operation.
b. Write 0x17 for Three-out-of-Six Decode operation.
c. Write 0x26 for Manchester Encode operation.
d. Write 0x27 for Three-out-of-Six Encode operation.
8. Wait on the DMA interrupt.
9. Clear the DMA enables in the DMA0EN SFR.
10. Clear the DMA interrupts in the DMA0INT SFR.
11. For a decode operation only, check the ERROR bit in ENC0CN for a decode error.
Note that the encoder and all DMA channels should be configured for Big-Endian mode.
Rev. 1.0
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