C8051F960-B-GM Datasheet, PDF (260/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 19.1. PCLKACT: Peripheral Active Clock Enable
Bit
7
6
5
4
3
2
1
0
Name
PCLKACT[3:0]
Type R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xF5
Bit Name
Function
7:4 Unused Read = 0b; Write = don’t care.
3 PCLKACT3 Clock Enable Controls for Peripherals in Low Power Active Mode.
0: Clocks to the SmaRTClock, Pulse Counter, and PMU0 revert to the PCLKEN set-
ting in Low Power Active Mode.
1: Enable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Active
Mode.
2 PCLKACT2 Clock Enable Controls for Peripherals in Low Power Active Mode.
0: Clocks to Timer 0, Timer 1, Timer 2, and CRC0 revert to the PCLKEN setting in Low
Power Active Mode.
1: Enable clocks to Timer 0, Timer 1, Timer 2, and CRC0 in Low Power Active Mode.
1 PCLKACT1 Clock Enable Controls for Peripherals in Low Power Active Mode.
0: Clocks to ADC0 and PCA0 revert to the PCLKEN setting in Low Power Active
Mode.
1: Enable clocks to ADC0 and PCA0 in Low Power Active Mode.
0 PCLKACT0 Clock Enable Controls for Peripherals in Low Power Active Mode.
0: Clocks to UART0, Timer 3, SPI0, and the SMBus revert to the PCLKEN setting in
Low Power Active Mode.
1: Enable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Active
Mode.
260
Rev. 1.0