C8051F960-B-GM Datasheet, PDF (448/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL
10
TMOD
GCT TGCT T
A / 11A / 00
T T MM T T MM
E110E010
1
0
IT01CF
IIIIIIII
NNNNNNNN
11110000
PSSSPSSS
LLLLLLLL
210 210
Pre-scaled Clock
0
0
SYSCLK
1
1
T0
Crossbar
TR0
GATE0
TCLK
TL0
(8 bits)
INT0
IN0PL _XOR
TH0
(8 bits)
Reload
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Figure 32.2. T0 Mode 2 Block Diagram
32.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode set-
tings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,
configure it for Mode 3.
448
Rev. 1.0