C8051F960-B-GM Datasheet, PDF (172/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 13.1. CRC1CN: CRC1 Control
Bit
7
6
5
4
3
2
1
0
Name CLR
DMA
FLIP
INV
SEED
Type R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xBE; Not Bit-Addressable
Bit
Name
Function
7
CLR
Reset.
Setting this bit to 1 will reset the CRC module and set the CRC results SFR to
the seed value as specified by the SEED bit. The CRC module should be reset
before starting a new CRC.
This bit is self-clearing.
6:4
Reserved
3
DMA
DMA Mode.
Setting this bit will configure the CRC1 module for DMA mode.
Once a DMA channel has been configured to use accept peripheral requests
from CRC1, setting this bit will initiate a DMA CRC operation.
This bit should be cleared after each CRC DMA transfer.
2
FLIP
Flip.
Setting this bit will flip the contents of the 16-bit CRC result SFRs.
(CRC0OUTH:CRC0OUTL)
This operation is normally performed only on the final CRC results.
This bit should be cleared before starting a new CRC computation.
1
INV
Invert.
Setting this bit will invert the contents of the 16-bit CRC result SFR.
(CRC0OUTH:CRC0OUTL)
This operation is normally performed only on the final CRC results.
This bit should be cleared before starting a new CRC computation.
0
SEED
Seed Polarity.
If this bit is zero, a seed value or 0x0000 will be used.
If this bit is 1, a seed value of 0xFFFF will be used.
This bit should be set before setting the RST bit.
172
Rev. 1.0