C8051F960-B-GM Datasheet, PDF (304/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
24.2.6. Missing SmaRTClock Detector
The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN.6) to 1.
When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if
SmaRTClock oscillator remains high or low for more than 100 µs.
A SmaRTClock Missing Clock detector timeout can trigger an interrupt, wake the device from a low power
mode, or reset the device. See Section “17. Interrupt Handler” on page 232, Section “19. Power Manage-
ment” on page 257, and Section “22. Reset Sources” on page 278 for more information.
Note: The SmaRTClock Missing Clock Detector should be disabled when making changes to the oscillator settings in
RTC0XCN.
24.2.7. SmaRTClock Oscillator Crystal Valid Detector
The SmaRTClock oscillator crystal valid detector is an oscillation amplitude detector circuit used during
crystal startup to determine when oscillation has started and is nearly stable. The output of this detector
can be read from the CLKVLD bit (RTX0XCN.4).
Notes:
1. The CLKVLD bit has a blanking interval of 2 ms. During the first 2 ms after turning on the crystal oscillator, the
output of CLKVLD is not valid.
2. This SmaRTClock crystal valid detector (CLKVLD) is not intended for detecting an oscillator failure. The
missing SmaRTClock detector (CLKFAIL) should be used for this purpose.
3. The CLKVLD bit output is driven low when BIASX2 is disabled.
24.3. SmaRTClock Timer and Alarm Function
The SmaRTClock timer is a 32-bit counter that, when running (RTC0TR = 1), is incremented every
SmaRTClock oscillator cycle. The timer has an alarm function that can be set to generate an interrupt,
wake the device from a low power mode, or reset the device at a specific time. See Section “17. Interrupt
Handler” on page 232, Section “19. Power Management” on page 257, and Section “22. Reset Sources”
on page 278 for more information.
The SmaRTClock timer includes an Auto Reset feature, which automatically resets the timer to zero one
SmaRTClock cycle after the alarm 0 signal is deasserted. When using Auto Reset, the Alarm match value
should always be set to 2 counts less than the desired match value. When using the LFO in combination
with Auto Reset, the right-justified Alarm match value should be set to 4 counts less than the desired
match value. Auto Reset can be enabled by writing a 1 to ALRM (RTC0CN.2).
24.3.1. Setting and Reading the SmaRTClock Timer Value
The 32-bit SmaRTClock timer can be set or read using the six CAPTUREn internal registers. Note that the
timer does not need to be stopped before reading or setting its value. The following steps can be used to
set the timer value:
1. Write the desired 32-bit set value to the CAPTUREn registers.
2. Write 1 to RTC0SET. This will transfer the contents of the CAPTUREn registers to the SmaRTClock
timer.
3. Operation is complete when RTC0SET is cleared to 0 by hardware.
The following steps can be used to read the current timer value:
1. Write 1 to RTC0CAP. This will transfer the contents of the timer to the CAPTUREn registers.
2. Poll RTC0CAP until it is cleared to 0 by hardware.
3. A snapshot of the timer value can be read from the CAPTUREn registers
Notes:
1. If the system clock is faster than 4x the SmaRTClock, then the HSMODE bit should be set to allow the set and
capture operations to be concluded quickly (system clock used for transfers).
2. If the system clock is slower than 4x the SmaRTClock, then HSMODE should be set to zero, and RTC must be
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