C8051F960-B-GM Datasheet, PDF (321/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 25.1. PC0MD: PC0 Mode Configuration
Bit
7
6
5
4
3
2
1
0
Name PCMODE[1:0]
PCRATE[1:0] DUALCMPL STPCNTFLTR DUALSTCH
Type
R/W
R/W
R/W
R
R/W
R
Reset 0
0
0
0
0
1
0
0
SFR Address = 0xD9; SFR Page = 0x2
Bit
Name
Function
7:6 PCMODE[1:0] Counter Mode
00: Pulse Counter disabled.
01: Single Counter mode.
10: Dual Counter mode.
11: Quadrature Counter mode.
5:4 PCRATE[1:0] PC Sample Rate
00: 250 µs
01: 500 µs
10: 1 ms
11: 2 ms
3 Reserved
2 STPCNTFLTR Stop Counting on Flutter
(Only valid for quadrature counter mode and DUALSTCH off.)
0: Disabled.
1: Enabled.
1 DUALSTCH Dual Mode Switch During Flutter
(Only valid for quadrature counter mode.)
0: Disabled—quadrature mode remains set during flutter.
1: Enabled—quadrature mode changes to dual during flutter.
0 Reserved
Note that writing to this register will clear the counter registers PC0CTR0H:M:L and PC0CTR1H:M:L.
Rev. 1.0
321