C8051F960-B-GM Datasheet, PDF (302/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 24.2. SmaRTClock Load Capacitance Settings
LOADCAP
0000
0001
0010
0011
0100
0101
Crystal Load Capacitance
4.0 pF
4.5 pF
5.0 pF
5.5 pF
6.0 pF
6.5 pF
Equivalent Capacitance seen on
XTAL3 and XTAL4
8.0 pF
9.0 pF
10.0 pF
11.0 pF
12.0 pF
13.0 pF
0110
0111
1000
1001
1010
1011
7.0 pF
7.5 pF
8.0 pF
8.5 pF
9.0 pF
9.5 pF
14.0 pF
15.0 pF
16.0 pF
17.0 pF
18.0 pF
19.0 pF
1100
1101
1110
1111
10.5 pF
11.5 pF
12.5 pF
13.5 pF
21.0 pF
23.0 pF
25.0 pF
27.0 pF
24.2.5. Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling
Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in
order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects
when the oscillation amplitude has reached a point where it safe to reduce the drive current, therefore, it
may be enabled during crystal startup. It is recommended to enable Automatic Gain Control in most sys-
tems which use the SmaRTClock oscillator in Crystal Mode. The following are recommended crystal spec-
ifications and operating conditions when Automatic Gain Control is enabled:
 ESR < 50 k
 Load Capacitance < 10 pF
 Supply Voltage < 3.0 V
 Temperature > –20 °C
When using Automatic Gain Control, it is recommended to perform an oscillation robustness test to ensure
that the chosen crystal will oscillate under the worst case condition to which the system will be exposed.
The worst case condition that should result in the least robust oscillation is at the following system condi-
tions: lowest temperature, highest supply voltage, highest ESR, highest load capacitance, and lowest bias
current (AGC enabled, Bias Double Disabled).
To perform the oscillation robustness test, the SmaRTClock oscillator should be enabled and selected as
the system clock source. Next, the SYSCLK signal should be routed to a port pin configured as a push-pull
digital output. The positive duty cycle of the output clock can be used as an indicator of oscillation robust-
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Rev. 1.0