C8051F960-B-GM Datasheet, PDF (435/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
31.10. Slave Mode DMA Transfers
SPI1 also supports using the DMA with Slave mode. The maximum SPI bit rate for a bidirectional Slave
mode transfer is SYSCLK/10.
In master mode, the master is responsible for initiating the transfer, clocking the data, managing the NSS
pin, and has control over the number of bytes transferred. In slave mode, the slave depends on the master
for the clock and NSS signal. The slave also depends on the master to set the time between bytes and the
number of bytes per transfer.
Firmware implementations of a SPI slave often have some restrictions on the time between bytes. When
using SPI0 in slave mode, an interrupt service routine commonly processes each byte received. This
imposes a limitation on the time between bytes. When using the SPI in Slave mode with the DMA, the time
between bytes must be long enough to accommodate the DMA latency.
The time between bytes in master mode and the minimum time required between bytes in slave mode will
depend on the DMA latency. The DMA latency will depend on a number of factors - the CPU state, the
number of active DMA channels, and the DMA channel priority. Using only the two required DMA channels
and putting the CPU in Idle mode will provide the lowest latency. If the CPU is actively executing instruc-
tions, the DMA may have to wait for the current instruction to execute before it can complete a transfer. If
other DMA channels are active, the SPI DMA channels may have to wait for other DMA transfers to com-
plete. This could be a very long time for long DMA transfers. Assigning the SPI to the first two DMA chan-
nels will ensure they have the highest DMA priority.
Note that in master mode, the time between bytes may prolong the DMA transfer, but does not usually
result in data loss. In slave mode, the slave may drop data if the DMA cannot keep up with the master data
coming in. Since the SPI slave data rate is limited to SYSCLK/10 and the longest instruction is 8 clock
cycles, a delay between bytes of one SPI clock will prevent data loss. Using a SPI DMA slave with addi-
tional active DMA channels may result in data loss and is not recommended.
31.11. Bidirectional SPI Slave Mode DMA Transfer
A bidirectional SPI Slave mode DMA transfer will transfer a specified number of bytes out on the MISO pin
and also receive the same number of bytes on the MOSI pin. The MISO data must be stored in XRAM
before initiating the DMA transfers. After the complete transfer, the MOSI data will be stored in XRAM.
Since the MISO data must be stored in XRAM before the transfer, the MISO data is fixed and should not
depend on the MOSI data received in the same transfer. The protocol designer should carefully consider
this behavior when designing a SPI slave protocol. Firmware can easily modify the MISO data after each
message. For example, one message can request data and a second message can read the data previ-
ously requested. This approach is much simpler and more efficient than attempting to modify the MISO
data buffer on-the-fly.
If the slave transfer is a fixed constant length, the DMA interrupt will indicate one complete transfer. Firm-
ware may implement a variable length slave transfer using an external interrupt connected to the NSS sig-
nal. In this case, firmware may use the DMA interrupt for a buffer overflow condition.
Rev. 1.0
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