C8051F960-B-GM Datasheet, PDF (353/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
27.1.3. Interfacing Port I/O to High Voltage Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage up to VBAT + 2.0 V. An external pull-up resistor to the higher supply voltage is typically
required for most systems.
27.1.4. Increasing Port I/O Drive Strength
Port I/O output drivers support a high and low drive strength; the default is low drive strength. The drive
strength of a Port I/O can be configured using the PnDRV registers. See Section “4. Electrical Characteris-
tics” on page 56 for the difference in output drive strength between the two modes.
27.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P2.6 can be assigned to various analog, digital, and external interrupt functions. The
Port pins assigned to analog functions should be configured for analog I/O and Port pins assigned to digital
or external interrupt functions should be configured for digital I/O.
27.2.1. Assigning Port I/O Pins to Analog Functions
Table 27.1 shows all available analog functions that need Port I/O assignments. Port pins selected for
these analog functions should have their digital drivers disabled (PnMDOUT.n = 0 and Port Latch =
1) and their corresponding bit in PnSKIP set to 1. This reserves the pin for use by the analog function
and does not allow it to be claimed by the Crossbar. Table 27.1 shows the potential mapping of Port I/O to
each analog function.
Table 27.1. Port I/O Assignment for Analog Functions
Analog Function
ADC Input
Comparator0 Input
Comparator1 Input
LCD Pins (LCD0)
Pulse Counter (PC0)
Voltage Reference (VREF0)
Analog Ground Reference (AGND)
Current Reference (IREF0)
External Oscillator Input (XTAL1)
External Oscillator Output (XTAL2)
SmaRTClock Input (XTAL3)
SmaRTClock Output (XTAL4)
Potentially
Assignable Port Pins
P0.0–P0.7,
P1.4–P2.3
P0.0–P0.7,
P1.4–P2.3
P0.0–P0.7,
P1.4–P2.3
P2.4–P6.7
P1.0, P1.1
P0.0
P0.1
P0.7
P0.2
P0.3
P1.2
P1.3
SFR(s) used for
Assignment
ADC0MX, PnSKIP
CPT0MX, PnSKIP
CPT1MX, PnSKIP
PnMDIN, PnSKIP
P1MDIN, PnSKIP
REF0CN, PnSKIP
REF0CN, PnSKIP
IREF0CN, PnSKIP
OSCXCN, PnSKIP
OSCXCN, PnSKIP
P1MDIN, PnSKIP
P1MDIN, PnSKIP
Rev. 1.0
353