C8051F960-B-GM Datasheet, PDF (456/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
When Capture Mode is enabled, a capture event will be generated either every Comparator 0 rising edge
or every 8 SmaRTClock clock cycles, depending on the T2XCLK1 setting. When the capture event occurs,
the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2 reload registers
(TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 interrupts are enabled).
By recording the difference between two successive timer capture values, the Comparator 0 or SmaRT-
Clock period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster
than the capture clock to achieve an accurate reading.
For example, if T2ML = 1b, T2XCLK1 = 0b, and TF2CEN = 1b, Timer 2 will clock every SYSCLK and cap-
ture every SmaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two
successive captures is 5984, then the SmaRTClock clock is as follows:
24.5 MHz/(5984/8) = 0.032754 MHz or 32.754 kHz.
This mode allows software to determine the exact SmaRTClock frequency in self-oscillate mode and the
time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the capaci-
tance of a Touch Sense Switch.
T2XCLK[1:0]
SYSCLK / 12
CKCON
TTTTTTSS
3 3 2 2 1 0CC
X0 M M M M M M A A
HLHL 10
Comparator 0
01
SmaRTClock / 8
11
0
TR2
SYSCLK
1
TCLK _{TMR2L TMR2H}
Capture
T2XCLK1
SmaRTClock / 8
0
Comparator 0
1
TF2CEN
TMR2RLL TMR2RLH
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK1
T2XCLK0
Figure 32.6. Timer 2 Capture Mode Block Diagram
Interrupt
456
Rev. 1.0