C8051F960-B-GM Datasheet, PDF (329/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 25.13. PC0CMP0H: PC0 Comparator 0 High (MSB)
Bit
7
6
5
4
3
2
1
0
Name
PC0CMP0H[23:16]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE3; SFR Page = 0x2
Bit
Name
Function
7:0 PC0CMP0H[23:16] PC0 Comparator 0 High Byte
Bits 23:16 of Counter 0.
SFR Definition 25.14. PC0CMP0M: PC0 Comparator 0 Middle
Bit
7
6
5
4
3
2
1
0
Name
PC0CMP0M[15:8]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE2; SFR Page = 0x2
Bit
Name
Function
7:0 PC0CMP0M[15:8] PC0 Comparator 0 Middle Byte
Bits 15:8 of Counter 0.
SFR Definition 25.15. PC0CMP0L: PC0 Comparator 0 Low (LSB)
Bit
7
6
5
4
3
2
1
0
Name
PC0CMP0L[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE1; SFR Page = 0x2
Bit
Name
Function
7:0 PC0CMP0L[7:0] PC0 Comparator 0 Low Byte
Bits 7:0 of Counter 0.
Note: PC0CMP0L must be written last after writing PC0CMP0M and PC0CMP0H. After writing PC0CMP0L, the
synchronization into the PC clock domain can take 2 RTC clock cycles.
Rev. 1.0
329