C8051F960-B-GM Datasheet, PDF (234/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Interrupt Source
Table 17.1. Interrupt Summary
Interrupt Priority
Vector Order
Pending Flag
Enable
Flag
Priority
Control
Reset
0x0000
External Interrupt 0 (INT0) 0x0003
Timer 0 Overflow
0x000B
External Interrupt 1 (INT1) 0x0013
Timer 1 Overflow
0x001B
UART0
0x0023
Timer 2 Overflow
0x002B
SPI0
0x0033
SMB0
0x003B
SmaRTClock Alarm
0x0043
ADC0 Window Compara-
tor
ADC0 End of Conversion
0x004B
0x0053
Programmable Counter
Array
Comparator0
0x005B
0x0063
Comparator1
0x006B
Timer 3 Overflow
0x0073
VDD/VBAT Supply Monitor 0x007B
Early Warning
Port Match
0x0083
Top
None
N/A N/A Always Always
Enabled Highest
0
IE0 (TCON.1)
Y Y EX0 (IE.0) PX0 (IP.0)
1
TF0 (TCON.5)
Y Y ET0 (IE.1) PT0 (IP.1)
2
IE1 (TCON.3)
Y Y EX1 (IE.2) PX1 (IP.2)
3
TF1 (TCON.7)
Y Y ET1 (IE.3) PT1 (IP.3)
4
RI0 (SCON0.0)
Y N ES0 (IE.4) PS0 (IP.4)
TI0 (SCON0.1)
5
TF2H (TMR2CN.7) Y N ET2 (IE.5) PT2 (IP.5)
TF2L (TMR2CN.6)
6
SPIF (SPI0CN.7) Y N ESPI0
WCOL (SPI0CN.6)
(IE.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
PSPI0
(IP.6)
7
SI (SMB0CN.0)
Y N ESMB0 PSMB0
(EIE1.0) (EIP1.0)
8 ALRM (RTC0CN.2)* N N EARTC0 PARTC0
(EIE1.1) (EIP1.1)
9
AD0WINT
Y N EWADC0 PWADC0
(ADC0CN.3)
(EIE1.2) (EIP1.2)
10 AD0INT (ADC0STA.5) Y N EADC0 PADC0
(EIE1.3) (EIP1.3)
11
CF (PCA0CN.7) Y N EPCA0 PPCA0
CCFn (PCA0CN.n)
(EIE1.4) (EIP1.4)
12 CP0FIF (CPT0CN.4) N N ECP0
PCP0
CP0RIF (CPT0CN.5)
(EIE1.5) (EIP1.5)
13 CP1FIF (CPT1CN.4) N N ECP1
PCP1
CP1RIF (CPT1CN.5)
(EIE1.6) (EIP1.6)
14
TF3H (TMR3CN.7) N N
ET3
PT3
TF3L (TMR3CN.6)
(EIE1.7) ^(EIP1.7)
15 VDDOK (VDM0CN.5)¹
VBOK (VDM0CN.2)¹
EWARN PWARN
(EIE2.0) (EIP2.0)
16
None
EMAT
PMAT
(EIE2.1) (EIP2.1)
234
Rev. 1.0