C8051F960-B-GM Datasheet, PDF (397/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
RA
Data Byte
A
Data Byte
NP
Interrupts with Hardware ACK Disabled (EHACK = 0)
Received by SMBus
Interface
Transmitted by
SMBus Interface
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Figure 28.8. Typical Slave Read Sequence
28.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 28.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 28.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ-
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allowed by hardware but do not conform to the SMBus specification.
Rev. 1.0
397