C8051F960-B-GM Datasheet, PDF (125/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
selection of bits in the PSBANK register, as described in SFR Definition 9.1. All other devices with 64 kB or
less program memory can be used as non-banked devices.
The IFBANK bits select which of the upper banks are used for code execution, while the COBANK bits
select the bank to be used for direct writes and reads of the flash memory.
A note about code banking and the "MOVC A, @A+PC" opcode: The MOVC A, @A+PC opcode uses the
COBANK bits to generate the effective address. Most compilers expect the reference from this instruction
to be relative to the Program Counter, which uses the IFBANK bits to generate the effective address. To
avoid incorrect device behavior, we recommend that IFBANK and COBANK be set to the same value in
systems that use (or may use) the "MOVC A, @A+PC" opcode.
The address 0x1FFFF (C8051F960/1/2/3), 0xFFFF (C8051F964/5), 0x07FFF (C8051F966/7), or 0x3FFF
(C8051F968/9) serves as the security lock byte for the device. Any addresses above the lock byte are
reserved.
C8051F960/1/2/3
Lock Byte
Lock Byte
Page
0x1FFFF
0x1FFFE
0x1FC00
0x1FBFF
Flash
Memory
Space
0x0000
C8051F964/5
C8051F966/7
C8051F968/9
Lock Byte 0x0FFFF
Lock Byte
Page
0x0FFFE
0x0FC00
0x0FBFF
Flash
Memory
Space
0x0000
Lock Byte
Lock Byte
Page
Flash
Memory
Space
0x07FFF
0x7FFE
0x07C00
0x07BFF
0x00000
Lock Byte
Lock Byte
Page
Flash
Memory
Space
0x03FFF
0x3FFE
0x03C00
0x03BFF
0x00000
Figure 9.2. Flash Program Memory Map
Rev. 1.0
125