C8051F960-B-GM Datasheet, PDF (29/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
1.2. Port Input/Output
Digital and analog resources are available through 57 I/O pins (C8051F960/2/4/6/8) or 34 I/O pins
(C8051F961/3/5/7/9). Port pins are organized as eight byte-wide ports. Port pins can be defined as digital
or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general
purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P7.0 can be used as GPIO
and is shared with the C2 Interface Data signal (C2D). See Section “34. C2 Interface” on page 486 for
more details.
The designer has complete control over which digital and analog functions are assigned to individual port
pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See
Section “27. Port Input/Output” on page 351 for more information on the Crossbar.
For Port I/Os configured as push-pull outputs, current is sourced from the VIO, VIORF, or VBAT supply pin.
Port I/Os used for analog functions can operate up to the supply voltage. See Section “27. Port Input/Out-
put” on page 351 for more information on Port I/O operating modes and the electrical specifications chap-
ter for detailed electrical specifications.
Highest
Priority
Lowest
Priority
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
XBR0, XBR1,
XBR2, PnSKIP
Registers
PnMDOUT,
PnMDIN Registers
External Interrupts
EX0 and EX1
2
UART
SPI0
4
SPI1
2
SMBus
CP0
4
CP1
Outputs
SYSCLK
PCA
7
2
T0, T1
Priority
8
Decoder
8
8
Digital
Crossbar
8
8
P0
I/O
Cells
P1
I/O
Cells
P2
I/O
Cells
P3
I/O
Cells
P4
I/O
Cells
8
P0
8
P5
I/O
Cells
8
P6 ^(P6.0-P6.7)
8
P6
I/O
Cells
1
P7
(P7.0)
1
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
P7
To EMIF
Figure 1.11. Port I/O Functional Block Diagram
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
P5.0
P5.7
P6.0
P6.7
P7.0
To LCD
Rev. 1.0
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